1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronics layers within microelectronics fabrications. More particularly, the present invention relates to selective methods for fabricating microelectronics layers within microelectronics fabrications.
2. Description of the Related Art
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become increasingly important within advanced microelectronics fabrications to form within advanced microelectronics fabrications high areal density patterned conductor layers (ie: patterned conductor layers having linewidth and pitch dimensions of less than about 0.40 microns) which have interposed between their patterns low dielectric constant dielectric layers. High areal density patterned conductor layers which have interposed between their patterns within advanced microelectronics fabrications low dielectric constant dielectric layers are desirable since there may then be fabricated within those advanced microelectronics fabrications electronics circuits which exhibit attenuated electronics circuit cross-talk, increased electronics circuit speed and other desirable electronics circuit properties.
While high areal density patterned conductor layers which have interposed between their patterns within advanced microelectronics fabrications low dielectric constant dielectric layers are thus desirable within the art of advanced microelectronics fabrication, fabrication of those low dielectric constant dielectric layers interposed between the patterns of high areal density patterned conductor layers within advanced microelectronics fabrications nonetheless presents practical problems within advanced microelectronics fabrication. In particular, it is known in the art of microelectronics fabrication that low dielectric constant dielectric materials from which may be formed low dielectric constant dielectric layers are typically either: (1) aerogel materials, or (2) materials which have a substantial organic content, such as but not limited to organic polymer materials and organo-functional siloxane spin-on-glass (SOG) materials. While the presence of such aerogel materials, organic polymer materials or organo-functional siloxane spin-on-glass (SOG) materials is desirable interposed between the patterns of high areal density patterned conductor layers within an advanced microelectronics fabrication, their presence is typically undesirable within locations other than those interposed between the patterns of high areal density patterned conductor layers within an advanced microelectronics fabrication, since such aerogel materials, organic polymer materials or organo functional siloxane spin-on-glass (SOG) materials typically also have in addition to low dielectric constants moisture sorbtion characteristics and other physical characteristics which compromise the reliability or functionality of a microelectronics fabrication within which is formed a low dielectric constant dielectric layer from an aerogel material, an organic polymer material or an organo-functional siloxane spin-on-glass (SOG) material.
It is thus desirable within the art of microelectronics fabrication to provide methods and materials through which there may be formed selectively interposed between the high areal density patterns of a high areal density patterned conductor layer a low dielectric constant dielectric layer while avoiding forming additional regions of the low dielectric constant dielectric layer upon portions of the microelectronics fabrication other than those interposed between the high areal density patterns of the high areal density patterned conductor layer. It is towards that goal that the present invention is specifically directed.
In a more general sense, it is also desirable within the art of microelectronics fabrication to provide methods and materials through which there may be formed selectively interposed between a plurality of horizontally closely spaced (ie: horizontal separation distance of less than about 0.40 microns) patterned microelectronics structures within a microelectronics fabrication a first region of an overlying microelectronics layer while avoiding forming an additional second region of the overlying microelectronics layer upon a portion of the microelectronics fabrication other than the first region interposed between the plurality of horizontally closely spaced patterned microelectronics structures. It is towards that goal that the present invention is more generally directed.
Various novel methods have been disclosed in the art of microelectronics fabrication for forming microelectronics layers, such as but not limited to low dielectric constant spin-on-glass (SOG) dielectric layers, within microelectronics fabrications. For example, U.S. Pat. No. 5,192,697 to Leong discloses an ion implantation method for curing a spin-on-glass (SOG) dielectric layer within an integrated circuit microelectronics fabrication. In comparison with conventional thermal curing methods, the ion implantation curing method provides a spin-on-glass (SOG) dielectric layer with a reduced concentration of entrapped gases remaining therein.
Similarly, U.S. Pat. No. 5,459,086 to Yang discloses an analogous ion implantation method for modifying within an integrated circuit microelectronics fabrication exposed spin-on-glass (SOG) dielectric layer sidewall surfaces within a via formed through a spin-on-glass (SOG) dielectric layer within the integrated circuit microelectronics fabrication. The ion implantation method employs a tilt angle with respect to the spin-on-glass (SOG) dielectric layer to provide exposed spin-on-glass (SOG) dielectric layer sidewall surfaces which are modified to attenuate moisture sorbtion and outgassing which would otherwise impede formation of a low resistance metal conductor stud layer within the via.
In addition, U.S. Pat. No. 5,366,910 to Ha et al. discloses a method for fabricating within an integrated circuit microelectronics fabrication a thin film transistor (TFT) having a spin-on-glass (SOG) layer formed thereover, where the spin-on-glass (SOG) layer is subsequently treated with an oxygen plasma. The oxygen plasma treatment of the spin-on-glass (SOG) layer increases the hydrogen content within the spin-on-glass (SOG) layer, thus stabilizing through hydrogen diffusion a polysilicon layer employed within the channel region of the thin film transistor (TFT).
Finally, U.S. Pat. No. 5,370,779 to Ohba et al. discloses an electron cyclotron resonance (ECR) plasma method for fabricating a microelectronics layer within a microelectronics fabrication, where the electron cyclotron resonance (ECR) plasma method employs a rotating magnetic field either parallel, perpendicular or both parallel and perpendicular to a microwave propagation direction within an electron cyclotron resonance (ECR) plasma employed within the electron cyclotron resonance (ECR) plasma method. Within the method, an ion beam derived from the electron cyclotron resonance (ECR) plasma is converged in part by applying a pulse voltage to the rotating magnetic field, thus providing an electron cyclotron resonance (ECR) plasma method through which the microelectronics layer may be precisely patterned.
Desirable within the art of microelectronics fabrication are methods and materials through which there may be formed selectively interposed between a plurality of horizontally closely spaced patterned microelectronics structures within a microelectronics fabrication a first region of an overlying microelectronics layer while avoiding forming an additional second region of the overlying microelectronics layer upon portions of the microelectronics fabrication other than those interposed between the plurality of horizontally closely spaced patterned microelectronics structures. More particularly desirable within the art of microelectronics fabrication are methods and materials through which there may be formed selectively interposed between the patterns of a high areal density patterned conductor layer a low dielectric constant dielectric layer while avoiding forming additional regions of the low dielectric constant dielectric layer upon portions of the microelectronics fabrication other than those interposed between the high areal density patterns of the high areal density patterned conductor layer. It is towards the foregoing goals that the present invention is both generally and specifically directed.